1. Field of the Invention
The present invention relates to a digital delay-locked loop (DLL) circuit.
2. Description of the Related Art
A prior art digital DDL circuit is constructed by a variable delay circuit formed by an inverter chain for delaying an input signal to generate an output signal, a phase comparator for comparing the phase of a feedback signal with the phase of a reference signal, and a ring counter for adjusting the delay time of the delay circuit. Thus, the delay time of the delay circuit is controlled in accordance with the output of the phase comparator, so that the difference in phase between the feedback signal and the reference signal is brought close to zero. This will be explained later in detail.
In the above-described prior art digital DDL circuit however, since the accuracy of the delay time of the variable delay circuit is determined by the value defined by two inverters of the inverter chain, it is impossible to carry out a more fine delay time control, which increases jitter in the output signal.
Also, if the accuracy of the delay time of the variable delay circuit is improved by dereasing the delay time of each inverter, it will take a longer locking time.
Therefore, in the prior art digital DDL circuit, the decrease of jitter has a trade-off relationship to the decrease of the locking time.
Further, in order to enlarge the range of the delay time of the variable delay circuit, if the inverter chain is lengthened, a selector for selecting the inverter chain is also increased in size, which increases the delay time of the selector. As a result, the minimum delay time of the variable delay circuit is increased. Further, the longer inverter chain will take a longer locking time.
Additionally, if the difference in phase between the feedback signal and the reference signal is smaller than xe2x88x92180 xc2x0 or larger than +180xc2x0, it is impossible to correctly lock the feedback signal to the reference signal.
It is an object of the present invention to provide a digital DDL circuit capable of decreasing jitter as well as decreasing the locking time.
Another object is to correctly lock a feedback signal to a reference signal even if the difference in phase is large.
According to the present invention, in a digital delay-locked loop circuit, a variable delay circuit for delaying an input signal and generating an output signal includes a first variable delay circuit for delaying the input signal with a first delay time changed at first intervals and a second variable delay circuit for delaying the input signal with a second delay time changed at second intervals smaller than the first intervals. A phase comparator compares the phase of a feedback signal derived from the output signal with the phase of the reference signal. A counter circuit controls the first and second delay times in accordance with a difference in phase between the feedback signal and the reference signal so that the difference in phase is brought close to zero.